With increasing recording densities in recording units represented by hard disk drives, various technologies have been devised. In particular, about a recording and reproducing method, the PRML has become generally in use to which technologies in communication field are applied.
The partial response (PR) is a system of reproducing data by actively making use of inter-symbol interference (ISI)(interference between regenerated signals corresponding to bits recorded adjacent to each other) with a necessary signal bandwidth compressed. The system may be further classified into a plurality of classes depending on the way of generating this inter-symbol interference. A PR target for magnetic recording is based on the PR in class 4 (PR4).
In addition, among decoding methods, the Viterbi decoding (ML) is a kind of maximum likelihood sequence estimation system which carries out data regeneration on the basis of information of signal gains over a plurality of time units by effectively making use of disciplined ISI (Inter-Symbol-Interference) of regenerated waveforms.
A system of regenerating data by combining the above described PR and ML is named as PRML.
The above-described PRML are provided in a number of variations depending on disciplined ISI of given waveforms. In particular, in the magnetic disk drive, used are such systems as PRML, EPRML (Extended PRML), EEPRML (Extended EPRML), and MEEPRML (Modified EEPRML).
A digital data regenerating apparatus using the PRML like the above is disclosed in, for example, JP-A-8-287607. In general, in a magnetic disc drive, information in magnetized form is read out as electric signals to be outputted as digitized information by a data regenerating circuit.
Processing corresponding to the above-described PRML is carried out in the data regenerating circuit. A read-back signal, being inputted to the data regenerating circuit, is appropriately processed before being converted to a digital signal by an analog to digital converter. A sampling clock for the conversion is generated in a synchronous signal generation circuit.
The synchronous signal generation circuit is constituted to have a phase error detector, a loop filter, and a VCO. The phase error detector obtains phase error between phases of a sampling timing of a sampled signal and an originally expected correct sampling timing. The loop filter carries out appropriate filtering processing of the obtained phase error signal. The VCO generates the sampling clock while controlling its oscillation frequency on the basis of the output signal of the loop filter.
Here, it is necessary for the synchronous signal generation circuit to generate from the generated signal itself a highly accurate sampling clock in synchronism with the regenerated signal. Moreover, by making the phase error detector provided with a high performance, data regenerating performance can be improved and faulty locking of the synchronous signal can be prevented. Such a phase error detector is disclosed in, for example, JP-A-10-125008 or JP-A-7-192406.